This invention relates to oxides grown on the surface of a substrate, more specifically to epitaxial oxides grown on the surface of semiconductors, and to the interface formed between the oxide and the semiconductor.
Ever since the first integrated circuit was demonstrated, one goal of the electronics industry has been to increase the density of individual devices in an integrated circuit. The smaller the device, the faster the conduction across the device. Ultimately, as smaller devices are made, the devices can be packed more densely, which reduces transmission between devices and also allows for faster operation.
Metal oxide semiconductor (MOS) technology forms the basis for a large part of chip manufacturing. In typical MOS transistor technology, SiO2 is grown so as to form part of a metal oxide semiconductor gate. SiO2 SO formed is commonly referred to as a gate oxide or a gate oxide dielectric. Until the time of this invention, SiO2 grown on MOS transistor gates has always been thought of as amorphous with little ordering in the first atomic layers at the interface between the silicon substrate and the oxide layer.
When the semiconductor material is not silicon, i.e., it is one of the multi-element semiconductors (e.g. SixGe1xe2x88x92x or GaAs) or germanium, the growth of an oxide layer is problematic. For instance, a multi-element semiconductor containing Si, when exposed to oxidation, tends to form a silicon oxide material at the surface, but below the silicon oxide layer the other material becomes more prevalent at the interface since the silicon there is depleted by its reaction with oxygen to form the oxide. This creates defects and changes the electrical characteristics of the interface.
Silicon has deficiencies as a semiconductor material when compared to some multi-element semiconductor material. However, silicon is used commercially as a semiconductor preferentially over other materials because it readily forms stable oxide dielectric layers with a lower interface defect density than other semiconductors and their oxides. The stability of Si/SiO2 having a low interface defect density enables the manufacture of transistors with better electrical properties than is attainable with other semiconductors.
The desire for lower dimension devices presents a basic problem: as devices get smaller in three dimensions, the dielectric layer must get both narrower and thinner and continue to function as a dielectric. Silicon does not always provide the optimum physical and electronic properties, such as a low interface defect density or a high dielectric constant, necessary to or tailored to fill a particular need. A desire for materials that have better tailored physical and electronic properties creates another problem: growth of dielectric layers on multi-element semiconductors is difficult. These two problems become essentially insurmountable when one desires a small device made out of a semiconductor other than doped silicon. Conceptually, a solution would lie in producing either a well-ordered ultra-thin oxide on top of the multi-element semiconductor, or at least a more ordered interface between the semiconductor and the dielectric layers. Doing so without elemental or phase separation is extremely difficult especially in chemical systems where the defect generation rate is higher than silicon, and as the physical sizes involved approach atomic dimensions. Any improvement in ordering at the interface or in the material will improve the interface defect density. It will be appreciated that, as smaller devices demand thinner dielectric layers, interface characteristics become increasingly important.
Another goal of electronic device processing is the growth of heterodielectrics or other materials listed below on a semiconductor substrate. While this goal is achievable for some systems, in general, growth of ordered films of a material on a semiconductor substrate is difficult.
FIG. 1A shows a diagram depicting a gate structure, a common configuration of components in a semiconductor device, in conjunction with an energy diagram 190. This diagram illustrates the relative energies for several critical parameters: the conduction band (Ec), the intrinsic Fermi level (EF,i), the Fermi level (Ef) and the valence band (Ec). In this figure SiO2 (171) is exhibiting an ideal interface with silicon. The defect-free interface does not capture electrons in the conduction path 175 of the p-type semiconductor 177. The energy diagram 190 clearly shows that the bands are flat for ideal SiO2.
FIG. 1B also depicts the arrangement as described in FIG. 1A. In this case, SiO2 179 has defects. These defects cause the bands to bend as seen in 192, for example electrons 181 (represented as minus signs) along the SiO2/Si interface can be captured by these defects, thus decreasing conduction in the n-channel 177.
In FIG. 1C, a voltage is applied to the gate structure 183. Though the SiO2/Si interface 185 has defects, the applied voltage, Vgate, attracts electrons at the SiO2/Si interface 185, and fills the defects (also called electron traps) at the interface. Therefore, extra conduction electrons can then flow unhindered, furthermore the bands now appear flat.
Disordered interface layers in the interfacial region, as discussed above, bring forth several effects. Disorder increases the interface defect density which causes a change in the electronic structure of the bands at the interface; the bands bend. The bands in the material form from the overlap of each constituent atom""s atomic orbitals. In a defect-free, non-molecular three dimensional solid, continuous bands can extend across the entire solid. In this case, a conduction band would provide a continuous path across the material. See FIG. 1A.
Any defect, such as a dislocation or a point, line, or planar defect, in the solid or at an interface, breaks the continuous nature of the bands because the energy of electronic orbitals of atoms on one side of the defect no longer align with the energy of orbitals of atoms on the other. This difference in alignment in the relative energies of the orbitals results in different energy levels for the overlapping orbitals. The energy levels of the continuous bands are defined by the degree of local overlap between the atomic orbitals. When the defect is an elemental impurity, the situation is more complicated. Explained simplistically, the orbitals of the impurity atom occupy different energy levels which cause the electrons to occupy energy levels outside of the bands. Because of the manner in which the atomic levels combine to form bands, the local perturbation in energy levels for dislocations and impurity defects or any type of point, line or planar defects, as described above, results in a local perturbation of the energy levels inside or outside of the bands. Extra, discreet energy levels appear which can result in band bending. See FIG. 1B. Band bending, because it provides additional energy levels in the conduction or the valence bands, can trap conduction electrons or holes. Electrical carriers are referred to as trapped because, in addition to the electrical force generated by the applied potential that causes conduction, an additional potential must also be applied to dislodge these trapped electrons and cause them to move.
To an extent, the interface between the dielectric layer on the surface of a semiconductor and the semiconductor itself acts like a defect. While it provides a discontinuity in the conduction band itself, the interface, if not ideal or perfect, causes the conduction band in the semiconductor material to be perturbed and therefore, produces band bending. Defects in the dielectric near the interface can also perturb the bands in the semiconductor. Band bending at the interface interferes with the flow of conduction electrons in the region of the semiconductor material immediately below the interface. As devices made from semiconductors become smaller, the interference with conduction caused by band bending becomes more important as described below.
To enable the defect containing material to function as a semiconductor, the trapping caused by band bending must be overcome regardless of whether the defect is due to dislocations, impurities, or any point, line, or planar defects or due to a layer of dielectric on the surface and the interface it forms. To a large extent in semiconductor materials, this is accomplished by producing very pure, highly crystalline materials and ultraclean, impurity-free interfaces. However, those methods do not deal with band bending caused by the intrinsic defect density of the interface between the dielectric and semiconductor material. Currently, this interface band bending is overcome by applying a voltage known as the flat band voltage. This voltage realigns the bands back to a flat condition, exactly compensating for band perturbations caused by any types of defects in the interfacial region. When the semiconductor material is part of a transistor, the flat-band voltage must be applied in addition to any control voltage used to operate the transistor. See FIG. 1C. Therefore, a device with a poorer electronic structure at the interface has a larger necessary bias voltage and higher power consumption. The need for the application of a larger bias voltage in addition to the control voltage increases the net voltage applied to the dielectric film. However, the thinner the film, the lower the voltage it can sustain. Thus, smaller transistor dimensions require minimizing or decreasing this voltage so as not to exceed the breakdown voltage of the thin oxide. Furthermore, a higher defect density at the interface results in more locations to pin conduction electrons, thereby decreasing the rate at which electrons can cross the device. The ideal interface structure has a low interface defect density, a low flat-band voltage, and a low fixed charge. A better, though heretofore unachieved, solution to band bending caused by the interfacial region is to grow an interface that has a structure commensurate with that of the semiconductor. The more the interfacial region looks like the semiconductor, from the point of view of the atomic levels on the semiconductor atoms, the less band bending. Creating a gradual change in the nature of the structure in the interfacial region causes less severe band bending. Another way to achieve this is to create an interface that has decreased interface defect density as compared to a conventional oxide. In other words, the growth of a more commensurate oxide or the formation of a more commensurate interface region, independent of the bulk oxide phase, results in an improvement of the interface defect density and of the ensuing electronic properties such as the flat band voltage, etc.
To minimize the interface defect density, considerable attention has been given to the surface treatment of the crystalline semiconductor wafers from which chips are formed. A typical RCA clean consists of degreasing the surface of the wafer in an oxidizing, basic solution such as 4-5:1:1 H2O: H2O2: NH4OH followed by an ionic clean/etch with a HF solution. The use of this cleaning step is an attempt at improving the quality of the interface by removing first organic impurities, and then metallic impurities.
As the art of electronics is currently practiced, the use of smaller dimensions for devices in silicon and especially the use of smaller devices for multi-element semiconductor materials is severely hampered by the quality of dielectric layers that can be formed. Also, the growth of heterodielectics on semiconductor substrates is also very difficult. What is needed is a method for growing more ordered layers of dielectrics and other material on the surfaces of semiconductors such as Si, SixGe1xe2x88x92x, GaAs, Si1xe2x88x92xxe2x88x92yGexCy, Si3(1xe2x88x92x)Ge3xN4(1xe2x88x92xcex4), Ge, SixGe(1xe2x88x92x)(OyN1xe2x88x92y)n, Si1xe2x88x92xxe2x88x92yGexCy(OzN1xe2x88x92z)n and (Si1xe2x88x92xxe2x88x92yGexCy)3N4xe2x88x92xxe2x88x92y, and GaAlAs. Another need is a method that will allow the growth of heterodielectrics and other materials such as CaF2, BaF2, SrTiO3, Pb(Zr,Ti)O3, BaTiO3, Zr(Ca)O2, Zr(Y)O2, LiNbO3, (LiNbO3, SrTiO3), (Zrxe2x80x94Ca)O2, Zr(Y)O2), GaAs, Ga2O3, As2O5, CdTe, InP, ZnSe, ZnS, HgCdTe, GaSb, InSb, Yttrium Barium Copper Oxide, Lanthanum Strontium Copper Oxide and Barium Europium Copper Oxide on the surface of a semiconductor substrate while substantially segregating the substrate from the overlayer.
In accordance with the invention, a method of producing ultra-thin films of a dielectric material on the surface of a substrate comprises the steps of creating a clean, atomically smooth (thus planar) surface on the substrate while simultaneously lowering the chemical reactivity of the surface so that any surface layer that forms naturally or is caused to form does so in a more ordered fashion than in conventional oxides producing a higher quality interface between the substrate surface and the growing layer. One embodiment comprises the steps of degreasing the surface of the substrate, then etching any native oxide off of the surface of the substrate, reoxidizing the surface of the substrate, and etching while passivating the surface of the substrate. Optionally, a final oxidation step can be employed. The invention consists of creating an interface surface phase with low defect density, and optionally an oxide layer on top of it, either conventionally grown or ordered.
The invention also includes an interface phase and/or a dielectric material produced using the above-mentioned method, a semiconductor device having a dielectric produced using the above-mentioned method, and the dielectric composition of matter so-produced.
In one embodiment of the process, according to the invention, the substrate is prepared (either mechanically or chemically) to be very smooth on the atomic level (one surface atomic step per 100-200 xc3x85 linear distance, compared to one atomic step per 10-20 xc3x85 as is common in the art), while simultaneously removing the native oxide coating that exists on virtually all substrates (element or alloy-like), removing most organic and metallic impurities, and then coating the surface of the substrate with an ultra-thin oxide-based dielectric or other surface coating which greatly retards the regrowth of the native oxide or other oxygen containing surface species. The resulting slow film growth and the extremely flat substrate surface combine synergistically to create an interface phase with an overlaid dielectric film comparable or better in dielectric quality to the very best dielectric films prepared commercially, but also much thinner and capable of being grown on most main group semiconductor substrates.
The dielectric layer thus-formed may be as thin as one half to ten nm. The process may include a preliminary degreasing step. An etching step may provide the smoothness and oxide and impurity removal. A primary oxidation step and a passivation step may provide the ultra-thin oxide-based coating or interface phase. Optionally, a final oxidation step may be employed. One of the main prerequisites in achieving an ultra-thin film dielectric is beginning with a substrate surface that is predominately smooth on the atomic level. Once the surface of the substrate is properly smoothed and passivated, then almost any well-known oxidation method will produce a high quality dielectric layer on top of the interface phase because the preparation and passivation steps promote slow growth of the oxide layer in well-known oxidation processes. In fact, if the surface is properly smoothed and cleaned, the passivation step itself will result in an interface phase suitable for use in microelectronic devices. The steps, called pre-passivation steps, of degreasing, etching, and primary oxidation create an atomically smooth, clean surface or a surface whose smoothness is improved as compared to conventional processes. This yields an interface phase with a lower interface defect density.
When it is desired to form thicker dielectric layers, the final oxidation step is employed. The prior surface preparation is still necessary even when a thicker layer is needed because the surface preparation seems to be the key factor in forming an interface phase that is more ordered and has a lower interface defect density as compared to conventional oxides. By making the surface smooth, the surface preparation forms an appropriate foundation for an interface that has a low interface defect density with some degree of higher order than conventional oxides. This interface phase then can seed the growth of a suitable oxide layer of increased thickness.
In the case of a silicon containing substrate, when a final oxidation step is not used, the surface prepared in accordance with the invention comprises an interface phase containing at least silicon, oxygen and hydrogen in an undetermined stoichiometry. When a final oxidation step is used, the surface is substantially SiO2. The final oxidation step results in an interface phase buried underneath an overlayer of SiO2. However, the interface phase between the SiO2 layer and the substrate is still believed to comprise silicon, oxygen and hydrogen. Because the atomic structures of silicon-containing substrates and SiO2 are dissimilar, the structure of the interface layer must bridge between that of the silicon-containing substrate and that of SiO2 by being substantially compatible with the structure of the silicon substrate on one side and SiO2 on the other. In making the transition between silicon and SiO2, there will invariably be instances of empty oxygen and silicon valence bonds. By the processes of this invention, it is believed that a hydrogen component serves to fill empty silicon or oxygen valence bonds at the interface. Furthermore, both infrared spectroscopy and ion beam analysis indicate the presence of silicon, oxygen and hydrogen at the interface. The actual bonding configuration of this interface phase has an infrared spectroscopic signature that does not include silicon hydride absorptions.
Dielectric films of between one or two atomic layers to 20 nanometers have been grown on a substrate, specifically, the surface of Si(100). The thinnest films are grown at room temperature by exposure to ambient air after passivation (i.e. simple exposure to oxygen gas), or in the passivation solution itself, or in a furnace at high temperature with low oxygen flow and a high nitrogen flow, or at temperatures below the oxidation temperature for silicon below 850xc2x0 C. Passivation slows the rate of oxide formation, so that a higher quality interface phase forms. All well known commercial oxidation processes can function as the final oxidation step in the practice of this invention including rapid thermal oxidation, furnace oxidation, high pressure oxidation and room temperature oxidation.
In connection with this invention, certain terms are used that are believed to be understood by those skilled in the art. xe2x80x9cLong range orderingxe2x80x9d is an expression that means, in contradistinction to xe2x80x9cshort range ordering,xe2x80x9d a regularity in the location of the atoms in a structure, such as a crystalline structure such that the location of an atom can be accurately predicted three, four, or more positions distant from a known atom location.
xe2x80x9cUltra-thin,xe2x80x9d as used herein, means having a thickness of 40 xc3x85 or less.
xe2x80x9cInterface defect densityxe2x80x9d is an expression used to mean a density of surface defects such atomic steps, missing atoms, or the presences of unfilled bonds. xe2x80x9cLowxe2x80x9d interface density is interface density lower than that achieved in prior procedures, all other variables being equal.
By xe2x80x9clow flat-band voltagexe2x80x9d is meant a flat-band voltage lower than that experienced in devices prepared using conventional semiconductor wafer cleaning and preparation, all other variables being equal.
xe2x80x9cHigh capacitancexe2x80x9d means a capacitance achieved that is higher than that achieved by dielectrics using conventional semiconductor wafer cleaning and preparation, all other variables being equal.